The present disclosure herein relates to an electronic device, and more particularly, to a fully parallel fast Fourier transformer used in an orthogonal frequency-division multiplexing system (OFDM) for fast optical communication.
Due to various advantages, the wide use of an OFDM scheme is a trend in a broadcast system, a wireless transmission/reception system, and a wired transmission/reception system such as an optical communication system. In an OFDM modulation/demodulation scheme, a fast Fourier transformer is a very important element.
A method for designing a fast Fourier transformer is very diversified but divided largely into a scheme formed of a single memory and a pipeline scheme formed of a plurality of memories and a plurality of processors. The scheme using the single memory uses an architecture including a radix-r processor and the single memory having the N-word size corresponding to the length of fast Fourier transform (FFT). For the case where the single memory is used, an in-place algorithm is required to be used. In an in-place scheme, a single memory having an address size as long as the length of FFT is given. In addition, data is read at a specific address, subjected to a radix-r operation and then stored again in a memory space having the same address. Since such an operation uses a single radix-r operator, the entire operation time increases with the length of FFT and the number of stages. However, the use of the single radix-r operator has an advantage in terms of the circuit size. The architecture based on the single memory is advantageous in a low hardware cost and easiness of low power implementation. Such an FFT architecture is suitable for an application field requiring a relative small bandwidth and a low throughput.
The pipeline FFT scheme configured of a plurality of processors is a scheme in which there are a plurality of radix-r processors having buffers between processors and memories are respectively inserted between the radix-r processors. In the pipeline FFT scheme, the entire architecture is configured of a plurality of stages that are coupled in series to each other. Each stage is provided with a unique radix-r processor and includes a separate buffer for storing data. Accordingly, since each stage may operate independently in the pipeline FFT scheme, a plurality of radix-r operations may be simultaneously performed. Accordingly, the pipeline FFT scheme is the same as the in-place scheme in terms of memory use, but a throughput thereof is much higher than that of the in-place scheme since radix-r operations are performed simultaneously at respective stages. The pipeline FFT scheme provides a high throughput but is disadvantageous in that the hardware size becomes large, since the plurality of radix-r processors are required to be maintained. Accordingly, the pipeline FFT scheme is proper to an application field such as WLAN or LTE which requires fast processing.
In optical communication requiring a very high throughput for data transmission of 100 Gbps, a faster processing architecture than the pipeline FFT scheme is necessary. In order to achieve such a fast processing requirement, an FFT architecture having an arrangement scheme or a fully parallel architecture is being proposed. In such an architecture, FFT input samples are required to be input at the same time to be processed, and then output at the same time. However, since a very large number of hardware resources are necessary for this fully parallel architecture internally, optimization should be accompanied in terms of hardware area.